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1 LTC3717 sn3717 3717fs wide operating range, no r sense tm step-down controller for ddr/qdr memory termination n v out = 1/2 v in (supply splitter) n adjustable and symmetrical sink/source current limit up to 20a n 0.65% output voltage accuracy n up to 97% efficiency n no sense resistor required n ultrafast transient response n true current mode control n 2% to 90% duty cycle at 200khz n t on(min) 100ns n stable with ceramic c out n dual n-channel mosfet synchronous drive n power good output voltage monitor n wide v cc range: 4v to 36v n adjustable switching frequency up to 1.5mhz n output overvoltage protection n optional short-circuit shutdown timer n available in a 16-pin narrow ssop package n bus termination: ddr and qdr memory, sstl, hstl, ... n notebook computers, desktop servers n tracking power supply the ltc ? 3717 is a synchronous step-down switching regulator controller for double data rate (ddr) and quad data rate tm (qdr tm ) memory termination. the controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor. oper- ating frequency is selected by an external resistor and is compensated for variations in v in . forced continuous operation reduces noise and rf inter- ference. output voltage is internally set to half of v ref , which is user programmable. fault protection is provided by an output overvoltage comparator and optional short-circuit shutdown timer. soft-start capability for supply sequencing is accom- plished using an external timing capacitor. the regulator current limit level is symmetrical and user programmable. wide supply range allows operation from 4v to 36v at the v cc input. , ltc and lt are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, hitachi, idt, micron technology, inc. and samsung. figure 1. high efficiency ddr memory termination supply efficiency vs load current + d b cmdsh-3 d1 b320a l1 0.68 h c vcc 4.7 f c in 150 f 6.3v 2 v in 2.5v to 5.5v v out 1.25v 10a + + c out 180 f 4v 2 m2 si7840dp 3717 f01a m1 si7840dp r on 715k c ss 0.1 f i on v ref tg sw boost run/ss i th sgnd intv cc bg pgnd v fb pgood c b 0.22 f r c 20k LTC3717 c c 470pf 1 f v cc v cc 5v to 28v d2 b320a v dd = 2.5v load current (a) 0 efficiency (%) 3717 f01b 100 90 80 70 60 50 40 30 20 10 0 2 4 6 8 10 12 14 v in = 2.5v v in = 5v v out = 1.25v applicatio s u features typical applicatio u descriptio u
2 LTC3717 sn3717 3717fs (note 1) input supply voltage (v cc , i on ) .................36v to C 0.3v boosted topside driver supply voltage (boost) ................................................... 42v to C 0.3v sw voltage .................................................. 36v to C 5v extv cc , (boost C sw), run/ss, pgood voltages ....................................... 7v to C 0.3v v ref , v rng voltages ...............(intv cc + 0.3v) to C 0.3v i th , v fb voltages...................................... 2.7v to C 0.3v tg, bg, intv cc , extv cc peak currents .................... 2a tg, bg, intv cc , extv cc rms currents .............. 50ma operating ambient temperature range (note 4) ................................... C 40 c to 85 c junction temperature (note 2) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC3717egn consult ltc marketing for parts specified with wider operating temperature ranges. t jmax = 125 c, q ja = 130 c/ w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 15v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc gn part marking 3717 symbol parameter conditions min typ max units main control loop i q input dc supply current normal 1000 2000 m a shutdown supply current v run/ss = 0v 15 30 m a v fb feedback voltage accuracy i th = 1.2v (note 3), v ref = 2.4v C 0.65 0.65 % d v fb(linereg) feedback voltage line regulation v cc = 4v to 36v, i th = 1.2v (note 3) 0.002 %/v d v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) l C 0.05 C 0.3 % g m(ea) error amplifier transconductance i th = 1.2v (note 3) 0.93 1.13 1.33 ms t on on-time i on = 30 m a 186 233 280 ns i on = 60 m a 95 115 135 ns t on(min) minimum on-time i on = 180 m a 50 100 ns t off(min) minimum off-time i on = 30 m a 300 400 ns v sense(max) maximum current sense threshold (source) v rng = 1v, v fb = v ref/2 C 50mv l 108 135 162 mv v pgnd C v sw v rng = 0v, v fb = v ref/2 C 50mv l 76 95 114 mv v rng = intv cc , v fb = v ref/2 C 50mv l 148 185 222 mv v sense(min) minimum current sense threshold (sink) v rng = 1v, v fb = v ref/2 + 50mv l C 140 C 165 C 190 mv v pgnd C v sw v rng = 0v, v fb = v ref/2 + 50mv l C 97 C 115 C 133 mv v rng = intv cc , v fb = v ref/2 + 50mv l C 200 C 235 C 270 mv d v fb(ov) output overvoltage fault threshold 8 10 12 % d v fb(uv) output undervoltage fault threshold C 25 % v run/ss(on) run pin start threshold l 0.8 1.5 2 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 4 4.5 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 4.2 v i run/ss(c) soft-start charge current C 0.5 C 1.2 C3 m a i run/ss(d) soft-start discharge current 0.8 1.8 3 m a
3 LTC3717 sn3717 3717fs the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 15v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: LTC3717egn: t j = t a + (p d ? 130 c/w) note 3: the LTC3717 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 4: the LTC3717e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. symbol parameter conditions min typ max units v cc(uvlo) undervoltage lockout threshold v cc falling l 3.4 3.9 v v cc(uvlor) undervoltage lockout threshold v cc rising l 3.5 4 v tg r up tg driver pull-up on resistance tg high 2 3 w tg r down tg driver pull-down on resistance tg low 2 3 w bg r up bg driver pull-up on resistance bg high 3 4 w bg r down bg driver pull-down on resistance bg low 1 2 w tg t r tg rise time c load = 3300pf 20 ns tg t f tg fall time c load = 3300pf 20 ns bg t r bg rise time c load = 3300pf 20 ns bg t f bg fall time c load = 3300pf 20 ns internal v cc regulator v intvcc internal v cc voltage 6v < v cc < 30v, v extvcc = 4v l 4.7 5 5.3 v d v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v C 0.1 2% v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising l 4.5 4.7 v d v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 5v 150 300 mv d v extvcc(hys) extv cc switchover hysteresis 200 mv pgood output d v fbh pgood upper threshold v fb rising (0% = 1/3 v ref ) 8 10 12 % d v fbl pgood lower threshold v fb falling (0% = 1/3 v ref )C8C10C12% d v fb(hys) pgood hysteresis v fb returning (0% = 1/3 v ref )12% v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v
4 LTC3717 sn3717 3717fs typical perfor a ce characteristics uw load current (a) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 100 3717 g06 0.1 v in = 2.5v v out = 1.25v figure 1 circuit input voltage (v) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 v out /v in (%) 3717 g07 50.00 49.95 49.90 49.85 49.80 49.75 49.70 49.65 load = 0a load = 10a figure 1 circuit load = 1a 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 input voltage (v) frequency (khz) 3717 g08 450 400 350 300 250 200 150 100 50 0 load = 0a v out = 1.25v figure 1 circuit load = 10a load current (a) 0 1 2 3 4 5 6 7 8 910 ? v out /v out (%) 3717 g09 0 0.1 0.2 0.3 0.4 0.5 0.6 v in = 2.5v v out = 1.25v figure 1 circuit efficiency vs load current v out /v in tracking ratio vs input voltage frequency vs input voltage load regulation start-up response load-step transient v in = 2.5v 4ms/div 3718 g09.eps v out = 1.25v load = 0.2 w figure 1 circuit v in = 2.5v 20 m s/div 3718 g10.eps v out = 1.25v load = 500ma to 10a step figure 1 circuit v out 1v/div i l 2a/div v out 200mv/div i l 5a/div v on voltage (v) 0 on-time (ns) 400 600 3717 g11 200 0 1 2 3 1000 i ion = 30 a 800 temperature ( c) ?0 on-time (ns) 200 250 300 25 75 3717 g12 150 100 ?5 0 50 100 125 50 0 i ion = 30 a i on current ( a) 1 10 on-time (ns) 100 1k 10k 10 100 3717 g13 on-time vs v on voltage on-time vs temperature on-time vs i on current
5 LTC3717 sn3717 3717fs typical perfor a ce characteristics uw temperature ( c) ?0 3.0 run/ss threshold (v) 3.5 4.0 4.5 5.0 25 0 25 50 3717 g16 75 100 125 latchoff enable latchoff threshold temperature (c) ?0 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 25 0 25 50 3717 g17 75 100 125 v rng (v) 0.50 maximum current sense threshold (mv) 300 250 200 150 100 50 0 0.75 1.00 1.25 1.50 3717 g18 1.75 2.00 run/ss (v) 2.0 maximum current sense threshold (mv) 3.6 3717 g19 2.8 3.0 3.2 3.4 2.2 2.4 2.6 160 140 120 100 80 60 40 20 0 maximum current sense threshold vs v rng voltage maximum current sense threshold vs run/ss voltage, v rng = 1v run/ss latchoff thresholds vs temperature undervoltage lockout threshold vs temperature intv cc load current (ma) 0 ? intv cc (%) 0.2 0.1 0 40 3717 g14 0.3 0.4 0.5 10 20 30 50 temperature ( c) 50 ?5 ? fcb pin current ( a) 0 3 0 50 75 3717 g15 ? 2 1 25 100 125 pull-up current pull-down current intv cc load regulation run/ss latchoff thresholds vs temperature temperature ( c) maximum current sense threshold (mv) 70 180 160 140 120 100 80 60 40 20 0 3717 g20 ?0 130 ?0 ?0 10 30 50 90 110 temperature ( c) gm (ms) 70 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 3717 g21 ?0 130 ?0 ?0 10 30 50 90 110 error amplifier gm vs temperature maximum current sense threshold vs temperature, v rng = 1v
6 LTC3717 sn3717 3717fs uu u pi fu ctio s run/ss (pin 1): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/ m f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. pgood (pin 2): power good output. open drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. v rng (pin 3): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maxi- mum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to intv cc . i th (pin 4): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). sgnd (pin 5): signal ground. all small-signal compo- nents and compensation components should connect to this ground, which in turn connects to pgnd at one point. i on (pin 6): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb (pin 7): error amplifier feedback input. this pin connects to v out and divides its voltage to 2/3 ? v fb through precision internal resistors before it is applied to the input of the error amplifier. do not apply more than 1.5v on v fb . for higher output voltages, attach an external resistor r2 (1/2 ? r1 at v ref ) from v out to v fb . v ref (pin 8): positive input of internal error amplifier. this pin connects to an external reference and divides its voltage to 1/3 v ref through precision internal resisters before it is applied to the positive input of the error amplifier. reference voltage for output voltage, power good threshold, and short-circuit shutdown threshold. do not apply more than 3v on v ref . if higher voltages are used, connect an external resistor (r1 3 160k) from voltage reference to v ref . extv cc (pin 9): external v cc input. when extv cc ex- ceeds 4.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v cc . v cc (pin 10): bias input supply. 4v to 36v operating range. decouple this pin to pgnd with an rc filter (1 w , 0.1 m f). intv cc (pin 11): internal 5v regulator output. the driver and control circuits are powered from this voltage. de- couple this pin to power ground with a minimum of 4.7 m f low esr tantalum or ceramic capacitor. bg (pin 12): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . pgnd (pin 13): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c vcc and the (C) terminal of c in . sw (pin 14): switch node. the (C) terminal of the boot- strap capacitor c b connects here. this pin swings from a diode voltage drop below ground up to a diode voltage drop above v in . tg (pin 15): top gate drive. drives the top n-channel mosfet with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. boost (pin 16): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc .
7 LTC3717 sn3717 3717fs fu ctio al diagra u u w 1.4v 0.7v v rng 3 8 + + + + + 6 i on 9 extv cc 10 v cc r on 0.7v i ion t on = (10pf) r sq 20k i cmp i rev 5.7 a shdn switch logic bg on fcnt + 4.7v ov 1 240k q1 q2 0.6v v ref 4 i th r c c c1 ea ss + q5 4 run/ss c ss 1 3717 fd sgnd 5 run shdn 12 pgnd 13 pgood v fb 2 intv cc 11 sw 14 tg c b v in c in 15 boost 16 + + uv ov c vcc v out m2 m1 l1 c out + 1.192v bngp 5v reg 1.2 a 6v d b i thb 7 v ref 80k 40k intv cc 11 30 v ref 3 10 v ref 40k 20k
8 LTC3717 sn3717 3717fs operatio u main control loop the LTC3717 is a current mode controller for dc/dc step-down converters. in normal operation, the top mosfet is turned on for a fixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current com- parator i cmp trips, restarting the one-shot timer and initi- ating the next cycle. inductor current is determined by sensing the voltage between the pgnd and sw pins using the bottom mosfet on-resistance . the voltage on the i th pin sets the comparator threshold corresponding to in- ductor valley current. the error amplifier ea adjusts this i th voltage by comparing 2/3 of the feedback signal v fb from the output voltage with a reference equal to 1/3 of the v ref voltage. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. as a result in normal ddr operation v out is equal to 1/2 of the v ref voltage. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2 m a current source to charge up an external soft-start capacitor c ss . when this voltage reaches 1.5v, the controller turns on and begins switch- ing, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft-start current limit is removed. intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is re- charged from intv cc through an external schottky diode d b when the top mosfet is turned off. when the extv cc pin is grounded, an internal 5v low dropout regulator supplies the intv cc power from v cc . if extv cc rises above 4.7v, the internal regulator is turned off, and an internal switch connects extv cc to intv cc . this allows a high efficiency source connected to extv cc , such as an external 5v supply or a secondary output from the converter, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive. if the v cc voltage is low and intv cc drops below 3.4v, undervoltage lockout circuitry prevents the power switches from turning on. applicatio s i for atio wu uu the basic LTC3717 application circuit is shown in figure 1. external component selection is primarily deter- mined by the maximum load current and begins with the selection of the sense resistance and power mosfet switches. the LTC3717 uses the on-resistance of the syn- chronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across a sense resistance that appears between the pgnd and sw pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approxi- mately (0.13)v rng for sourcing current and (0.17)v rng for sinking current. the current mode control loop will not allow the inductor current valleys to exceed (0.13)v rng / r sense for sourcing and (0.17)v rng /r sense for sinking. in practice, one should allow some margin for variations in
9 LTC3717 sn3717 3717fs applicatio s i for atio wu uu the load current. during LTC3717s normal operation, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = the resulting power dissipation in the mosfets at maxi- mum output current are: p top = d top i out(max) 2 r t(top) r ds(on)(max) + k v in 2 i out(max) c rss f p bot = d bot i out(max) 2 r t(bot) r ds(on)(max) both mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are largest at high input voltages. the constant k = 1.7a C1 can be used to estimate the amount of transition loss. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. junction temperature ( c) ?0 r t normalized on-resistance 1.0 1.5 150 3717 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs. temperature operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of LTC3717 applications is deter- mined implicitly by the one-shot timer that controls the the LTC3717 and external component values and a good guide for selecting the sense resistance is: r v i sense rng out max = 10 () an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense voltage is about 1.3 times this nominal value for positive output current and 1.7 times the nominal value for negative output current. power mosfet selection the LTC3717 requires two external n-channel power mos- fets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v intv cc supply. consequently, logic-level threshold mosfets must be used in LTC3717 applications. if the input voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = r the r t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c as shown in figure 2. for a maximum junction temperature of 100 c, using a value r t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and
10 LTC3717 sn3717 3717fs applicatio s i for atio wu uu on-time t on of the top mosfet switch. the on-time is set by the current into the i on pin according to: t v i pf on ion = (. ) () 07 10 tying a resistor r on from v in to the i on pin yields an on- time inversely proportional to v in . for a step-down con- verter, this results in approximately constant frequency operation as the input supply varies: f v vr pf h out on z = (. ) ( ) [] 07 10 because the voltage at the i on pin is about 0.7v, the current into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. a more exact equation taking in account the 0.7v drop on the i on pin is: f vv v v r pf v h out in on in z = (.) (. ) ( ) [] 07 07 10 to correct for this error, an additional resistor r on2 connected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 07 = . inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: d= ? ? ? ? - ? ? ? ? i v fl v v l out out in 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l v fi v v out lmax out in max = ? ? ? ? - ? ? ? ? d () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. a variety of inductors designed for high current, low voltage applications are available from manu- facturers such as sumida, panasonic, coiltronics, coilcraft and toko. schottky diode d1 selection the schottky diode d1 shown in figure 1 conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omitted if the efficiency loss is tolerable. c in and c out selection the input capacitance c in is required to filter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out @ () 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple kool m m is a registered trademark of magnetics, inc.
11 LTC3717 sn3717 3717fs current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple d v out is approximately bounded by: dd + ? ? ? ? v i esr fc out l out 1 8 since d i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifi- cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5 m f to 50 m f aluminum electrolytic capacitor with an esr in the range of 0.5 w to 2 w . high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1 m f to 0.47 m f, x5r or x7r dielectric capacitor is adequate. fault condition: current limit the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the LTC3717, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limits are: i positive v r i limit sns max ds on t l =+d () () r 1 2 i negative v r i limit sns min ds on t l =d () () r 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of applicatio s i for atio wu uu
12 LTC3717 sn3717 3717fs time that the LTC3717 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 300ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + intv cc regulator an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the LTC3717. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7 m f tantalum or other low esr capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. applica- tions using large mosfets with a high input voltage and high frequency of operation may cause the LTC3717 to exceed its maximum junction temperature rating or rms current rating. most of the supply current drives the mosfet gates unless an external extv cc source is used. in continuous mode operation, this current is i gatechg = f(q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics. for example, the LTC3717cgn is limited to less than 14ma from a 30v supply: t j = 70 c + (14ma)(30v)(130 c/w) = 125 c for larger currents, consider using an external supply with the extv cc pin. extv cc connection the extv cc pin can be used to provide mosfet gate drive and control power from the output or another external source during normal operation. whenever the extv cc pin is above 4.7v the internal 5v regulator is shut off and an internal 50ma p-channel switch connects the extv cc pin to intv cc . intv cc power is supplied from extv cc until this pin drops below 4.5v. do not apply more than 7v to the extv cc pin and ensure that extv cc v cc . the follow- ing list summarizes the possible connections for extv cc : applicatio s i for atio wu uu 1. extv cc grounded. intv cc is always powered from the internal 5v regulator. 2. extv cc connected to an external supply. a high effi- ciency supply compatible with the mosfet gate drive requirements (typically 5v) can improve overall efficiency. 3. extv cc connected to an output derived boost network. the low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7v. the system will start-up using the internal linear regulator until the boosted output supply is available. external gate drive buffers the LTC3717 drivers are adequate for driving up to about 60nc into mosfet switches with rms currents of 50ma. applications with larger mosfet switches or operating at frequencies requiring greater rms currents will benefit from using external gate drive buffers such as the ltc1693. alternately, the external buffer circuit shown in figure 4 can be used. note that the bipolar devices reduce the signal swing at the mosfet gate, and benefit from an increased extv cc voltage of about 6v. figure 4. optional external gate driver q1 fmmt619 gate of m1 tg boost sw q2 fmmt720 q3 fmmt619 gate of m2 bg 3717 f04 intv cc pgnd q4 fmmt720 10 10 soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the LTC3717 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the LTC3717 into a low quiescent current shutdown (i q < 30 m a). releasing the pin allows an internal 1.2 m a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss = m =m () 15 12 13 . . ./
13 LTC3717 sn3717 3717fs applicatio s i for atio wu uu figure 5. run/ss pin interfacing with latchoff defeated when the voltage on run/ss reaches 1.5v, the LTC3717 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/ m f. the pin can be driven from logic as shown in figure 5. diode d1 reduces the start delay while allowing c ss to charge up slowly for the soft-start func- tion. after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8 m a cur- rent then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 3.5v, then the con- troller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. the overcurrent protection timer requires that the soft- start timing capacitor c ss be made large enough to guar- antee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1 m f is more than sufficient. overcurrent latchoff operation is not always needed or desired. the feature can be overridden by adding a pull- up current greater than 5 m a to the run/ss pin. the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 5a is simple, but slightly increases shutdown current. connecting a resistor to intv cc as shown in figure 5b eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to pull run/ss above the 4.5v maximum threshold that arms the latchoff circuit and overcome the 4 m a maximum discharge current. 3.3v or 5v run/ss v in intv cc run/ss d1 d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3717 f06 2n7002 (5a) (5b) efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3717 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 w and r l = 0.005 w , the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capaci- tance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss @ (1.7a C1 ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by supply- ing intv cc current through the extv cc pin from a high
14 LTC3717 sn3717 3717fs efficiency source, such as an output derived boost net- work or alternate supply if available. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. the i th pin external components shown in figure 6 will provide adequate compensation for most applica- tions. for a detailed explanation of switching control loop theory see application note 76. design example as a design example, take a supply with the following specifications: v in = v ref = 2.5v, v extvcc = 5v, v out = 1.25v 5%, i out(max) = 10a, f = 250khz. first, calculate the timing resistor with v on = v out : r vv v v khz pf v k on ==w 125 25 07 0 7 250 10 2 5 514 .(..) ( . )( )( ) . and choose the inductor for about 40% ripple current at the maximum v in : applicatio s i for atio wu uu l v khz a v v h =- ? ? ? ? =m 125 250 0 4 10 1 125 25 063 . ( )( . )( ) . . . selecting a standard value of 0.68 m h results in a maximum ripple current of: d= m ? ? ? ? = i v khz h v v a l 125 250 0 68 1 125 25 37 . ()(.) . . . next, choose the synchronous mosfet switch. choosing a si4874 (r ds(on) = 0.0083 w (nom) 0.010 w (max), q ja = 40 c/w) yields a nominal sense voltage of: v sns(nom) = (10a)(1.3)(0.0083 w ) = 108mv tying v rng to 1.1v will set the current sense voltage range for a nominal value of 110mv with current limit occurring at 143mv. to check if the current limit is acceptable, assume a junction temperature of about 40 c above a 70 c ambient with r 110 c = 1.4: i mv aa limit 3 w += 143 14 0010 1 2 3 7 12 1 (. )(. ) (. ) . and double check the assumed t j in the mosfet: p vv v aw bot =w= 25 125 25 12 1 1 4 0 010 1 02 2 .. . (.)(.)(. ) . t j = 70 c + (1.02w)(40 c/w) = 111 c because the top mosfet is on roughly the same amount of time as the bottom mosfet, the same si4874 can be used as the synchronous mosfet. the junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. c in is chosen for an rms current rating of about 5a at 85 c. the output capacitors are chosen for a low esr of 0.013 w to minimize output voltage changes due to induc- tor ripple current and load steps. for current sinking applications where current flows back to the input through the top transistor, output capacitors with a similar amount of bulk c and esr should be placed on the input as well.
15 LTC3717 sn3717 3717fs (this is typically the case, since v in is derived from another dc/dc converter.) the ripple voltage will be only: d v out(ripple) = d i l(max) (esr) = (4a) (0.013 w ) = 52mv however, a 0a to 10a load step will cause an output change of up to: d v out(step) = d i load (esr) = (10a) (0.013 w ) = 130mv an optional 22 m f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 6. pc board layout checklist when laying out a pc board follow one of the two sug- gested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. applicatio s i for atio wu uu ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. ? place LTC3717 chip with pins 9 to 16 facing the power components. keep the components connected to pins 1 to 8 close to LTC3717 (noise sensitive components). ? use an immediate via to connect the components to ground plane including sgnd and pgnd of LTC3717. use several bigger vias for power components. ? use compact plane for switch node (sw) to improve cooling of the mosfets and to keep emi down. ? use planes for v in and v out to maintain good voltage filtering and to keep power losses low. figure 6. design example: 1.25v/ 10a at 250khz 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc LTC3717 + m2 si4874 m1 si4874 l1 0.68 h d1 b320a d2 b320a c out1-2 270 f 2v 2 c out3 22 f 6.3v x7r c in 22 f 6.3v x7r v ext 5v v in = 2.5v v out 1.25v 10a c ss 0.1 f c c1 470pf c on 0.01 f c c2 100pf c vcc 4.7 f c f 0.1 f (opt) 0.1 f c b 0.22 f r c 20k r on 511k r f 1 d b cmdsh-3 3717 f06a c in , c out1-2 : cornell dubilier esre181e04b l1: sumida cep125-0r68mc-h r pg 100k r3 11k r4 39k + + c in 180 f 4v 2 10
16 LTC3717 sn3717 3717fs figure 7. LTC3717 layout diagram 16 15 14 13 12 11 10 9 c c2 bold lines indicate high current paths c c1 c ss c fb c ion r on r c r f 3717f07 1 2 3 4 5 6 7 8 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc c b m2 m1 d1 d2 d b c f c vcc c out c in v in v out + + LTC3717 l + applicatio s i for atio wu uu ? flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 7. ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. ? place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? connect the input capacitor(s) c in close to the power mosfets. this capacitor carries the mosfet ac cur- rent. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the v cc pin decoupling capacitor c f closely to the v cc and pgnd pins.
17 LTC3717 sn3717 3717fs 1.5v/ 10a at 300khz from 5v to 28v input 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc LTC3717 + m2 irf7822 m1 irf7811w l1 1.2 h d1 b320a b320a c out 270 f 2v 2 c in 10 f 35v 3 10 f 6.3v x7r v ref 3v v in 5v to 28v v out 1.5v 10a c ss 0.1 f c c1 680pf c on 0.01 f c c2 100pf c vcc 4.7 f c b 0.22 f r c 20k r on 510k d b cmdsh-3 3717 ta01 c out : cornell dubilier esre271m02b r pg 100k r r1 11k r r2 39k typical applicatio s u
18 LTC3717 sn3717 3717fs typical applicatio s u high voltage half (v in ) power supply 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc LTC3717 + m2 fds6680s m1 fds6680s l1 1.8 h c out1 270 f 16v c out2 10 f 15v c in 10 f 25v 2 v in 5v to 25v v out v in /2 6a c ss 0.1 f c c1 470pf c2 2200pf c on 0.01 f c c2 100pf c vcc 4.7 f c f 0.1 f c b 0.22 f r c 20k r on 510k r2 1m d b cmdsh-3 3717 ta02 c in : taiyo yuden tmk432bj106mm c out1 : sanyo, os-con 16sp270 c out2 : taiyo yuden jmk316bj106ml l1: toko 919as-1r8n r pg 100k r f 1 r1 2m
19 LTC3717 sn3717 3717fs package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
20 LTC3717 sn3717 3717fs part number description comments ltc1625/ltc1775 no r sense tm current mode synchronous step-down controller 97% efficiency; no sense resistor; 99% duty cycle ltc1628-pg dual, 2-phase synchronous step-down controller power good output; minimum input/output capacitors; 3.5v v in 36v ltc1628-sync dual, 2-phase synchronous step-down controller synchronizable 150khz to 300khz ltc1709-7 high efficiency, 2-phase synchronous step-down controller up to 42a output; 0.925v v out 2v with 5-bit vid ltc1709-8 high efficiency, 2-phase synchronous step-down controller up to 42a output; vrm 8.4; 1.3v v out 3.5v ltc1735 high efficiency, synchronous step-down controller burst mode tm operation; 16-pin narrow ssop; 3.5v v in 36v ltc1736 high efficiency, synchronous step-down controller with 5-bit vid mobile vid; 0.925v v out 2v; 3.5v v in 36v ltc1772 sot-23 step-down controller current mode; 550khz; very small solution size ltc1773 synchronous step-down controller up to 95% efficiency, 550khz, 2.65v v in 8.5v, 0.8v v out v in , synchronizable to 750khz ltc1778/ltc3778 wide operating range, no r sense step-down synchronous controllers 4v v in 36v, true current mode control, 2% to 90% duty cycle ltc1874 dual, step-down controller current mode; 550khz; small 16-pin ssop, v in < 9.8v ltc1876 2-phase, dual synchronous step-down controller with 2.6v v in 36v, power good output, step-up regulator 300khz operation ltc3413 monolithic ddr memory termination regulator 90% efficiency, 3a output, 2mhz operation burst mode is a registered trademark of linear technology corporation. ? linear technology corporation 2001 lt/tp 0103 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts u typical applicatio typical application 1.25v/ 3a at 1.4mhz 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 run/ss pgood v rng i th sgnd i on v fb v ref boost tg sw pgnd bg intv cc v cc extv cc LTC3717 + + m2 1/2 si9802 m1 1/2 si9802 l1 0.7 h c out 120 f 4v c in 120 f 4v v in 2.5v v out 1.25v 3a c ss 0.1 f c c1 470pf c on , 0.01 f c c2 100pf c vcc 4.7 f 1 f c b 0.22 f r c 33k r on 92k d b cmdsh-3 3717 ta03 c in , c out : cornell dubilier esrd121m04b l1: toko a921cy-0r7m r pg 100k 5v

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